In mobile systems-on-a-chip (SOC), chip performance is becoming increasingly important to benchmark against competition. The traditional approach is to design an integrated circuit (IC) using transistor models and simulate it at certain voltage, temperature, and process corners to ensure the IC meets certain performance criteria. Once design is complete, the IC is manufactured according to the transistor specifications used by the design. Thus, performance of the IC is fixed at the design operating conditions. However, customers continuously demand improvements in IC performance. It is highly desirable to have an IC that outperforms a competitor's product to differentiate over competitor devices. Conventional methods dictate that product improvement requires redesigning the entire IC. However, redesigning the entire IC requires very high reengineering costs and long cycle times. What is needed are IC design and fabrication techniques that increase IC performance without sacrificing standby (i.e., sleep-mode) leakage, and without requiring repetitive redesign of the entire IC.
Accordingly, there are long-felt industry needs for methods and apparatus that mitigate problems of conventional methods and apparatus, including selectively improving IC performance.